FIG. 21 schematically shows an illustrative structure of a DLL (delay lock loop) used e.g. in a conventional DDRII/I-SDRAM (Double Delta Rate II-Synchronous DRAM). Referring to FIG. 21, the DLL is made up by two control circuits and two coarse delay lines CDL 10 having a variable delay time. The control circuit is composed of a phase detector (P/D) 12, also termed a phase comparator, and a counter 13. An output of a receiver 11, which receives complementary clock signals CLK and CLKB, is supplied to the coarse delay line CDL 10, output pairs O0 and E0 of which are supplied to a fine delay line FDL 15, composed of a phase interpolator, for phase adjustment. A multiplexer 17 receives output data signals, not shown, in parallel, and selects and outputs the output data signal to a data terminal DQ, in synchronization with each of the rising edge and the falling edge of a clock signal CLK_0, output from the fine delay line FDL 15. Meanwhile, a reference numeral 17 in FIG. 21 collectively denotes a multiplexer (data multiplexer) for multiplexing input parallel data signals (read data) on a serial data signal, based on a clock signal CLK_0, and an output buffer for outputting data from a data output terminal DQ. A dummy circuit 18 is a dummy multiplexer for producing a delay equivalent to the delay time of the multiplexer 17 in the feedback route in the DLL circuit. The dummy circuit 18 outputs a feedback clock signal CLK_FDB which rises based on a rising edge of the clock signal CLK_0 and which falls based on a falling edge of the clock signal CLK_0. Meanwhile, an input of the phase detector (P/D) 12 may be an internal signal I0 and a dummy buffer of the delay time equivalent to that of the input buffer 11 may be provided between the dummy circuit 18 and the phase detector (P/D) 12. Alternatively, the feedback clock signal CLK_FDB may be delayed by the dummy circuit 18 by a delay value equivalent to the delay time of the input buffer 11.
The phase detector (P/D) 12 compares the phase of the feedback clock signal CLK_FDB, output from the dummy circuit 18, with the phase of the input signal CLK (e.g. phase of the rising edge), and counts the result of comparison from the phase detector (P/D) 12, with a counter 13, with the phase lead being UP and the phase delay being DOWN). A selection circuit 14 decodes the count result by the counter 13 to generate a control signal, used for variably setting the delay time in the coarse delay line CDL 10. Meanwhile, the phase interpolator of the fine delay line FDL 15 outputs an output signal of the phase (delay) prescribed by division of the phase difference (delay) of the inputs O0 and E0. It is noted that a pair of signals, entered to the phase interpolator, are represented by an even signal (E0 of FIG. 21) and an odd signal (O0 of FIG. 21).
In this DLL circuit, the propagation time of the data output DQ is synchronized with an integer number times one clock cycle time tCK of the input clock signal CLK. For example, if one clock period tCK is longer, as shown in FIG. 3A, the synchronization of the data DQ with the clock signal CLK is attained in one clock cycle (referred to as “1T mode”).
If one clock period tCK is lesser than the intrinsic delay of the delay circuit (smallest delay time), as shown in FIG. 3B, the synchronization of the data DQ with the clock signal CLK is attained in two clock cycles (referred to as “2T mode”).
In the DLL circuit, employing a CMOS delay circuit, the shorter the propagation time, the lesser become the timing variations relative to the variations in the power supply, that is, jitter. As for the timing variations, the following relation is valid:(timing variations)∝(propagation time)×(level variations) and(level variations)∝(current consumption)                where P∝Q means that P is proportionate to B.        
FIG. 23 is a diagram showing a structure of a conventional coarse delay line (CDL) used in the DLL circuit shown e.g. in FIG. 21. Meanwhile, as for the CDL, shown in FIG. 23, reference is made e.g. to the following Patent Publication 1. Referring to FIG. 23, the CDL includes a delay line circuit, composed of inverters 201, 202, . . . and 217, and first to eighth tristate inverters 221 to 228 which receive outputs of the odd-numbered stage inverters 201, 203, 205, . . . , and 215 respectively. Outputs of the first and third stage tristate inverters 221 and 223 are connected in common and supplied to the ninth tristate inverter 229. Outputs of the second and fourth stage tristate inverters 222 and 224 are connected in common and supplied to the tenth tristate inverter 230. Outputs of the fifth and seventh tri-state inverters 225 and 227 are connected in common and supplied to the eleventh tri-state inverter 231, while outputs of the sixth and eighth tri-state inverters 226 and 228 are connected in common and supplied to the twelfth tri-state inverter 232. Outputs of the ninth and eleventh tri-state inverters 229 and 231 are connected in common and supplied to the eleventh tri-state inverter 233, while outputs of the tenth and twelfth tri-state inverters 230 and 232 are connected in common and supplied to an inverter 234. The inverters 233 and 234 output an even output E0 and an odd output O0, respectively. The eleventh and twelfth tri-state inverters 231 and 232 have output control terminals for receiving the result of logical sum operations of RF_4 and RF_8 by an OR circuit 243 and the result of logical sum operations of RF_6 and RF_10 by an OR circuit 244 respectively, while the ninth and tenth tri-state inverters 229 and 230 have output control terminals for receiving the result of logical sum operations of RF_12 and RF_16 by an OR circuit 241 and the result of logical sum operations of RF_14 and RF_18 by an OR circuit 242 respectively.
Meanwhile, the specifications of e.g. the DDR (Double Data Rate)-II/I are such that the data output DQ is synchronized with both edges of a clock signal, and that the duty ratio of 45 to 55% is allowed for the input clock signal CLK. In order to make it possible to attain synchronization at the 1.5 clock cycle between the 1T mode and the 2T mode, it becomes necessary to independently set the delay time for the rise input and that for the fall input of the clock signals CLK in a DLL circuit or the like. However, in the conventional coarse delay line CDL, shown in FIGS. 21 and 23, it is not possible to set the rise or fall of the output clock signal independently from the rising edge and the falling edge of the input clock signal.
As a delay lock loop for independently setting the rise and falling edges of an output clock signal from the rise and falling edges of the input clock signal, respectively, there is known a configuration in which a coarse delay line CDL(R) 101 for rising edge adjustment and a coarse delay line CDL(L) 102 for falling edge adjustment, are provided, as shown for example in FIG. 22, and in which phase detectors 121 and 122 and counters 131 and 132 are also provided as the control circuit. Meanwhile, as for the structure in which a pair of coarse delay lines CDL are provided for the rising edge and the falling edge, reference is made to e.g. the following Patent Publication 2.
In FIG. 22, fine delay lines (FDL) 151 and 152 are provided in association with the coarse delay lines for rising edge adjustment CDL(R) 101 and with the coarse delay lines for falling edge adjustment CDL(L) 102, and there is provided a multiplexer circuit 16 for multiplexing two outputs of the fine delay lines (FDL) 151 and 152 into one signal. An output clock signal CLK_0 from the multiplexer circuit 16 is supplied to the data multiplexer 17 which outputs two data (readout data) per clock cycle from a data output terminal DQ, in synchronism with a rising edge and the falling edge of the clock signal CLK_0. Meanwhile, the reference numeral 17 in FIG. 22 indicates a data output route for e.g. the multiplexer and the output buffer.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2003-91331A (FIGS. 1 and 7)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-101409A (FIG. 20)